300 lines
11 KiB
Rust
300 lines
11 KiB
Rust
// Copyright (c) 2021 Weird Constructor <weirdconstructor@gmail.com>
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// This file is a part of HexoDSP. Released under GPL-3.0-or-later.
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// See README.md and COPYING for details.
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use crate::nodes::{NodeAudioContext, NodeExecContext};
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use crate::dsp::helpers::{TriggerPhaseClock, Trigger};
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use crate::dsp::{NodeId, SAtom, ProcBuf, DspNode, LedPhaseVals, NodeContext};
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use crate::dsp::tracker::TrackerBackend;
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use crate::dsp::MAX_BLOCK_SIZE;
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#[macro_export]
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macro_rules! fa_tseq_cmode { ($formatter: expr, $v: expr, $denorm_v: expr) => { {
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let s =
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match ($v.round() as usize) {
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0 => "RowT",
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1 => "PatT",
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2 => "Phase",
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_ => "?",
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};
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write!($formatter, "{}", s)
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} } }
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#[derive(Debug)]
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pub struct TSeqTime {
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clock: TriggerPhaseClock,
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trigger: Trigger,
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}
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/// A tracker based sequencer
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#[derive(Debug)]
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pub struct TSeq {
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backend: Option<Box<TrackerBackend>>,
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srate: f64,
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time: Box<TSeqTime>,
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}
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impl Clone for TSeq {
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fn clone(&self) -> Self { Self::new(&NodeId::Nop) }
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}
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impl TSeq {
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pub fn new(_nid: &NodeId) -> Self {
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Self {
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backend: None,
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srate: 48000.0,
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time: Box::new(TSeqTime {
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clock: TriggerPhaseClock::new(),
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trigger: Trigger::new(),
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}),
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}
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}
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pub fn set_backend(&mut self, backend: TrackerBackend) {
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self.backend = Some(Box::new(backend));
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}
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pub const clock : &'static str =
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"TSeq clock\nClock input\nRange: (0..1)\n";
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pub const trig : &'static str =
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"TSeq trig\nSynchronization trigger which restarts the sequence.\nRange: (-1..1)\n";
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pub const cmode : &'static str =
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"TSeq cmode\n'clock' input signal mode:\n\
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- RowT: Trigger = advance row\n\
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- PatT: Trigger = pattern rate\n\
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- Phase: Phase to pattern index\n\
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\n";
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pub const trk1 : &'static str =
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"TSeq trk1\nTrack 1 signal output\nRange: (-1..1)\n";
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pub const trk2 : &'static str =
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"TSeq trk2\nTrack 2 signal output\nRange: (-1..1)\n";
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pub const trk3 : &'static str =
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"TSeq trk3\nTrack 3 signal output\nRange: (-1..1)\n";
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pub const trk4 : &'static str =
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"TSeq trk4\nTrack 4 signal output\nRange: (-1..1)\n";
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pub const trk5 : &'static str =
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"TSeq trk5\nTrack 5 signal output\nRange: (-1..1)\n";
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pub const trk6 : &'static str =
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"TSeq trk6\nTrack 6 signal output\nRange: (-1..1)\n";
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pub const gat1 : &'static str =
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"TSeq gat1\nTrack 1 gate output\nRange: (-1..1)\n";
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pub const gat2 : &'static str =
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"TSeq gat2\nTrack 2 gate output\nRange: (-1..1)\n";
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pub const gat3 : &'static str =
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"TSeq gat3\nTrack 3 gate output\nRange: (-1..1)\n";
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pub const gat4 : &'static str =
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"TSeq gat4\nTrack 4 gate output\nRange: (-1..1)\n";
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pub const gat5 : &'static str =
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"TSeq gat5\nTrack 5 gate output\nRange: (-1..1)\n";
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pub const gat6 : &'static str =
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"TSeq gat6\nTrack 6 gate output\nRange: (-1..1)\n";
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pub const DESC : &'static str =
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"Tracker (based) Sequencer\n\n\
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This node implements a sequencer that can be programmed \
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using the tracker interface in HexoSynth on the right.\n\
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It provides 6 CV signal and 6 gate outputs.";
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pub const HELP : &'static str =
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r#"Tracker (based) Sequencer
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This sequencer gets it's speed from the clock source. The 'clock'
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signal can be interpreted in different modes. But if you want to
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run multiple sequencers in parallel, you want to synchronize them.
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For this you can use the 'trig' input, it resets the played row to
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the beginning of the sequence every time a trigger is received.
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Alternatively you can run the sequencer clock using the phase mode.
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With that the phase (0..1) signal on the 'clock' input determines the
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exact play head position in the pattern. With this you just need to
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synchronize the phase generators for different sequencers.
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For an idea how to chain multiple tracker sequencers, see the next page.
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This tracker provides 6 columns that each can have one of the following
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types:
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- Note column: for specifying pitches.
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- Step column: for specifying non interpolated CV signals.
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- Value column: for specifying linearly interpolated CV signals.
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- Gate column: for specifying gates, with probability and ratcheting.
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Step, value and gate cells can be set to 4096 (0xFFF) different values
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or contain nothing at all. For step and value columns these values
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are mapped to the 0.0-1.0 CV signal range, with 0xFFF being 1.0
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and 0x000 being 0.0.
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Value examples: 1.0 0.9 0.75 0.5 0.25 0.1
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0xFFF 0xE70 0xC00 0x800 0x400 0x19A
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Gate examples:
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Probability Ratcheting Gate Length full on gate: 0xFFF
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6% 0x000 16 0x000 1/16 0x000 2 short pulses: 0xFE0
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18% 0x200 14 0x020 3/16 0x002 4 short pulses: 0xFC0
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25% 0x300 13 0x030 4/16 0x003 2 50% pulses: 0xFE7
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50% 0x700 9 0x070 8/16 0x007 half on gate: 0xFF7
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62% 0x900 7 0x090 10/16 0x009 short pulse: 0xFF0
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75% 0xC00 4 0x0C0 12/16 0x00C rare short pulse: 0xEF0
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87% 0xE00 2 0x0E0 15/16 0x00E 50/50 short pulse: 0x7F0
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100% 0xF00 1 0x0F0 16/16 0x00F 50/50 full gate: 0x7FF
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On the next page you can read about the gate cells and the gate outputs.
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---page---
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Gate Input and Output
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The gate cells are differently coded:
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- 0x00F: The least significant nibble controls the gate length.
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With 0x00F being the full row, and 0x000 being 1/16th of a row.
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- 0x0F0: The second nibble controls ratcheting, with 0x0F0 being one
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gate per row, and 0x000 being 16 gates per row.
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Length of these gates is controlled by the last significant nibble.
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- 0xF00: The most significant nibble controls probability of the
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whole gate cell. With 0xF00 meaning the gate will always be
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triggered, and 0x000 means that the gate is only triggered with
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6% probability. 50% is 0x700.
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The behaviour of the 6 gate outputs of TSeq depend on the corresponding
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column type:
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- Step gat1-gat6: Like note columns, this will output a 1.0 for the whole
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row if a step value is set. With two step values directly
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following each other no 0.0 will be emitted in between
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the rows. This means if you want to drive an envelope
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with release phase with this signal, you need to make
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space for the release phase.
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- Note gat1-gat6: Behaves just like step columns.
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- Gate gat1-gat6: Behaves just like step columns.
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- Value gat1-gat6: Outputs a 1.0 value for the duration of the last row.
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You can use this to trigger other things once the
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sequence has been played.
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Tip:
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If you want to use the end of a tracker sequence as trigger for
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something else, eg. switching to a different 'tseq' and restart
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it using it's 'trig' input, you will need to use the gate output
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of a value column and invert it.
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"#;
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}
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impl DspNode for TSeq {
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fn outputs() -> usize { 1 }
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fn set_sample_rate(&mut self, srate: f32) {
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self.srate = srate as f64;
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}
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fn reset(&mut self) {
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self.backend = None;
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self.time.clock.reset();
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self.time.trigger.reset();
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}
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#[inline]
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fn process<T: NodeAudioContext>(
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&mut self, ctx: &mut T, _ectx: &mut NodeExecContext,
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_nctx: &NodeContext,
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atoms: &[SAtom], inputs: &[ProcBuf],
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outputs: &mut [ProcBuf], ctx_vals: LedPhaseVals)
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{
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use crate::dsp::{out, inp, at, denorm};
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let clock = inp::TSeq::clock(inputs);
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let trig = inp::TSeq::trig(inputs);
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let cmode = at::TSeq::cmode(atoms);
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let backend =
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if let Some(backend) = &mut self.backend {
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backend
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} else { return; };
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backend.check_updates();
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let mut phase_out : [f32; MAX_BLOCK_SIZE] =
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[0.0; MAX_BLOCK_SIZE];
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let cmode = cmode.i();
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let plen = backend.pattern_len().max(1) as f64;
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let time = &mut self.time;
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for frame in 0..ctx.nframes() {
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if time.trigger.check_trigger(
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denorm::TSeq::trig(trig, frame))
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{
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time.clock.sync();
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}
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let phase =
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match cmode {
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0 => time.clock.next_phase(plen, clock.read(frame)) / plen,
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1 => time.clock.next_phase(1.0, clock.read(frame)),
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2 | _ => (clock.read(frame).abs() as f64).fract(),
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};
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phase_out[frame] = phase as f32;
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}
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// println!("PHASE {}", phase_out[0]);
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let mut col_out : [f32; MAX_BLOCK_SIZE] =
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[0.0; MAX_BLOCK_SIZE];
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let mut col_out_gate : [f32; MAX_BLOCK_SIZE] =
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[0.0; MAX_BLOCK_SIZE];
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let col_out_slice = &mut col_out[ 0..ctx.nframes()];
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let col_out_gate_slice = &mut col_out_gate[0..ctx.nframes()];
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let phase_out_slice = &phase_out[ 0..ctx.nframes()];
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let out_t1 = out::TSeq::trk1(outputs);
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backend.get_col_at_phase(
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0, phase_out_slice, col_out_slice, col_out_gate_slice);
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out_t1.write_from(col_out_slice);
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let out_g1 = out::TSeq::gat1(outputs);
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out_g1.write_from(col_out_gate_slice);
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ctx_vals[0].set(col_out_slice[col_out_slice.len() - 1]);
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let out_t2 = out::TSeq::trk2(outputs);
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backend.get_col_at_phase(
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1, phase_out_slice, col_out_slice, col_out_gate_slice);
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out_t2.write_from(col_out_slice);
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let out_g2 = out::TSeq::gat2(outputs);
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out_g2.write_from(col_out_gate_slice);
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let out_t3 = out::TSeq::trk3(outputs);
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backend.get_col_at_phase(
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2, phase_out_slice, col_out_slice, col_out_gate_slice);
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out_t3.write_from(col_out_slice);
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let out_g3 = out::TSeq::gat3(outputs);
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out_g3.write_from(col_out_gate_slice);
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let out_t4 = out::TSeq::trk4(outputs);
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backend.get_col_at_phase(
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3, phase_out_slice, col_out_slice, col_out_gate_slice);
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out_t4.write_from(col_out_slice);
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let out_g4 = out::TSeq::gat4(outputs);
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out_g4.write_from(col_out_gate_slice);
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let out_t5 = out::TSeq::trk5(outputs);
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backend.get_col_at_phase(
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4, phase_out_slice, col_out_slice, col_out_gate_slice);
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out_t5.write_from(col_out_slice);
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let out_g5 = out::TSeq::gat5(outputs);
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out_g5.write_from(col_out_gate_slice);
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let out_t6 = out::TSeq::trk6(outputs);
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backend.get_col_at_phase(
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5, phase_out_slice, col_out_slice, col_out_gate_slice);
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out_t6.write_from(col_out_slice);
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let out_g6 = out::TSeq::gat6(outputs);
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out_g6.write_from(col_out_gate_slice);
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ctx_vals[1].set(phase_out_slice[phase_out_slice.len() - 1]);
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}
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}
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